Network World

Cray to unite scalar, vector computer architectures

Cray plans to create a new supercomputing platform combining four types of processing capability in a blade server architecture. Cray Inc. plans to create a new supercomputing platform combining four ...
EDN

CPU IP processes mixed scalar and vector workloads

The SiFive Performance P570 Gen 3 is a RISC-V out-of-order superscalar vector processor IP designed for scalable performance. SiFive says it delivers a substantial performance improvement over the ...
EDN

AI is stress-testing processor architectures and RISC-V fits the moment

Every major computing era has been defined not by technology, but by a dominant workload—and by how well processor architectures adapted to it. The personal computer era rewarded general-purpose ...
Semiconductor Engineering

Multi-Core Architecture Optimized For Time-Predictable Neural Network Inference (FZI, KIT)

A new technical paper titled “MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference” was published by researchers at FZI Research Center for Information ...
Business Wire

SiFive Intelligence for Modern ML Architectures Presentation at Linley Spring Processor Conference

SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Chris Lattner, President of Engineering and ...