Intel, Cadence Design Systems Expand Collaboration

Cadence, a maker of chip design software, and Intel Foundry will collaborate on "Design Technology Co-Optimization" in a multi-year agreement beginning with Intel's upcoming 14A semiconductor ...
TMCnet

Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs

The DTCO collaboration focuses on optimizing tools, flows, and methodologies to deliver industry-leading performance, power, and area (PPA). Cadence and Intel will work closely to optimize Intel 14A ...
MarketWatch

(CNW) Imec mitigates thermal bottleneck in 3D HBM-on-GPU architectures using a system-technology co-optimization approach

-- Imec presents the first comprehensive thermal study of 3D HBM-on-GPU integration using a system-technology co-optimization (STCO) approach. -- The study allows to identify and mitigate thermal ...
Nasdaq

Ansys Strengthens Collaboration with TSMC on Advanced Node Processes Certification and 3D-IC Multiphysics Design Solutions

AI-based workflows aid advanced node designs, ensuring design and system technology co-optimization for HPC and AI applications / Key Highlights TSMC and Ansys advance AI-assisted workflows to support ...
Semiconductor Engineering

STCO for Dense Edge Architectures using 3D Integration and NVM (imec,, et al.)

A new technical paper titled “System-Technology Co-Optimization for Dense Edge Architectures using 3D Integration and Non-Volatile Memory” was published by researchers at imec, INESC-ID, Université ...
KVOA 4

Imec mitigates thermal bottleneck in 3D HBM-on-GPU architectures using a system-technology co-optimization approach

Holistic system-technology co-optimization (STCO) approach key in reducing peak GPU and HBM temperatures under AI workloads while enhancing performance density of future GPU-based architectures Imec ...